A Novel Low-Power Low-Voltage CMOS 1-Bit Full Adder Cell with the GDI Technique
نویسندگان
چکیده
The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power 1-bit full adder cell is proposed, where the GDI technique has been used for the simultaneous generation of XOR and XNOR functions. Simulation results are performed by HSPICE based on 0.18 m μ CMOS technology, shows that the new full adder circuit outstrips many latest designs in energy efficiency and has the lowest power-delay product over a wide range of voltages among several low-power adder cells of different CMOS logic styles.
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